The principle governing the operation of the memory cells in magnetic random access memory (MRAM) cells or bits is the change of resistivity of certain materials in the presence of a magnetic field (magneto-resistance). Magneto-resistance can be significantly increased by means of a structure known as a spin valve. The resulting increase (known as Giant Magneto-Resistance or GMR) derives from the fact that electrons in a magnetized solid are subject to significantly less scattering by the lattice when their own magnetization vectors (due to spin) are parallel (as opposed to anti-parallel) to the direction of magnetization of their environment.
The key elements of a spin valve are a low coercivity (free) ferromagnetic layer, a non-magnetic spacer layer, and a high coercivity ferromagnetic layer. The latter is usually formed out of a soft ferromagnetic layer that is pinned magnetically by an associated antiferromagnetic layer. When the free layer is exposed to an external magnetic field, the direction of its magnetization is free to rotate according to the direction of the external field. After the external field is removed, the magnetization of the free layer will stay at a direction, which is dictated by the minimum energy state, determined by the crystalline and shape anisotropy, coupling field and demagnetization field. If the magnetization direction of the pinned layer is parallel to the free layer, electrons passing between the free and pinned layers, suffer less scattering. Thus, the resistance at this state is lower, when current flows along the film plane. If, however, the magnetization of the pinned layer is anti-parallel to the free layer, electrons passing from one layer into the other will suffer more scattering so the resistance of the structure will increase. The change in resistance of spin valve is typically 8-15%.
This simple sandwich structure of ferromagnetic layer-thin conductor-ferromagnetic layer can be used as a memory element. In this structure, there is no anti-ferromagnetic layer, thus, neither of the two ferromagnetic layers is pinned. This kind of memory cell is called a pseudo-spin valve memory cell. Both are free to switch magnetization under external field. One of the ferromagnetic layers is thicker than the other, the thicker one switches magnetization direction at a higher external magnetic field.
However, of special interest for the present disclosure is the magnetic tunneling junction (MTJ) in which the layer that separates the free and pinned layers is a non-magnetic insulator, such as alumina or silica. Its thickness needs to be such that it will transmit a significant tunneling current. The principle governing the operation of the MTJ cell in MRAM arrays is the change of resistivity of the tunnel junction between two ferromagnetic layers. When the magnetization of the two ferromagnetic layers is in opposite directions, the tunneling resistance increases due to a reduction in the tunneling probability. The change of resistance is typically 40% for alumina tunnel junction and 200% for MgO, which is much larger than for GMR devices.
A typical magnetic tunnel junction device is made up of three basic layers. A top ferromagnetic (FM) layer, a tunnel oxide insulating layer and a bottom FM layer. The magnetization of the top FM layer is free to switch states while the bottom electrical conducting FM layer is pinned, usually by an antiferromagnetic (AF) material, such as PtMn or NiMn. Those layers that are below the tunnel junction are typically referred to as base layers. Depending on the order in which layers are deposited, the base layer could be a ferromagnetic layer on an antiferromagnetic layer on a seed layer or it could be a single ferromagnetic layer. Typically, the base layer is electrically conductive and the thickness of the base layer is less than 500 Å.
The cell states are programmed by applying an external magnetic field to switch the magnetization of the free layer. A current in the program line under a cell generates the program field. Conductive traces referred to as word lines and bit lines are routed across the array of memory cells. The word lines extend along rows of the memory cells and the bit lines extend along columns of the memory cells. A memory cell stores a bit of information as an orientation of magnetization in the sense layer at each intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer referred to as its “easy axis”. The orientation of magnetization does not easily align along an axis orthogonal to the easy axis, referred to as the “hard axis”. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer. The resistance through the memory cell differs according to the parallel or anti-parallel orientation of magnetization and is highest when the orientation is anti-parallel, i.e. one logic state, and lowest when the orientation is parallel, i.e. the other logic state.
A problem associated with the programming of MRAM devices has been that the required current is orders of magnitude larger than that needed for many other memory devices, such as static random access memory (SRAM) or dynamic random access memory (DRAM), being in the range of 6-10 mA. Furthermore, cell size does not scale with lithography. For such large program currents, the width of the program lines of the cell is much greater than the minimal wire widths allowed by the design rules. In addition, today's metal-oxide-semiconductor field effect transistors (MOSFETs) can only provide 0.2-0.5 mA for a gate width of 1 μm, so to switch a 10 mA current, a MOSFET must be designed with a gate width greater than 20 μm—which is too large for effective use of substrate real estate. Thus, it is very important to minimize the program current in MRAM arrays.